Many processing systems, such as numerical and video/graphics data processing systems, operate on sequences or streams of digital data words. For example, a typical graphics/video processing system processes sequences of pixel data words each of which defines the color or gray scale level of a corresponding pixel of a frame of pixels being displayed on a display screen. Normally, the words of pixel data defining a given frame are exchanged between the display controller, the frame buffer memory and the display in the same sequence such words will be required during the refresh of the corresponding pixels on the display screen. In numerical data processing applications, sequences of words of data may be generated, stored in memory and then sequentially retrieved when needed to perform a series of numerical calculations. In each case, it becomes critical that the time required to exchange such sequences of data between the processors and memory be minimized in order to optimize system performance.
Dynamic random access memory devices (DRAMs) are often used in the construction of sequentially accessed memory systems such as those discussed above. These devices typically store bits of data in dynamic storage cells arranged in an array of rows and columns. With this arrangement, the bits composing entire words of data can be stored in and retrieved from adjacent cells in the array--namely in adjacent cells along the same row. Page mode (burst mode) accessing is then typically used to access one or more words from a given row during a single address cycle to improve processing speed. During a DRAM page mode access (either a read or a write), a row address is presented to the device address port and latched in with a row address strobe (RAS) to select a given row in the array. A column address strobe is next presented to the address port and latched in with a column address strobe (CAS) to select a first column thereby allowing access to a first cell (bit) along the selected row. Column decode circuitry (static or dynamic) then increments from the received column address to generate a sequence of column addresses to adjacent columns, thereby allowing access to a sequence or "page" of cells (bits) from the selected row.
The page (burst) length of currently available DRAMs operating the page (burst) mode is partially limited by the available column address space. In other words, the number of bits which can be accessed as a single page is dependent on the number of column addresses which can be generated during a given address cycle. Once the column address space has been exhausted, a new row address must be presented and latched in with the falling edge of RAS (i.e., a new address cycle is initiated). In addition, a precharge must be performed between address cycles (i.e., when RAS is high) which requires additional time. Thus, with each new address cycle an access time penalty is paid.
With any memory system based on DRAMS, data refresh becomes an important consideration. Without periodic refresh, data (i.e., charge) being stored in dynamic memory cells may deteriorate or be lost completely. In the case of dynamic memory systems operating on blocks of data, such as DRAMs operating in a page or burst mode, it often becomes necessary to hold a block of data for a substantial period of time and consequently block refresh becomes necessary. Typically, each DRAM device is placed in a mode where a block are continually refreshed during a data storage period using a counter which generates row addresses by counting for each row from a column address minimum to a column address maximum. With each new row a complete RAS cycle must be performed (i.e. a new row address must be presented and latched in with RAS). With each new RAS cycle an access time penalty is paid.
Thus, the need has arisen for improved memory architectures, circuits and for methods of using the same which provide for the rapid refresh of blocks of data.